Conventional memory circuits which utilize static memory cells, such circuits including static random access memories (SRAMs), FIFOs, dual-port memories, and microprocessors and other logic devices with such memory embedded therein, are generally organized in rows and columns. In these conventional memories, a row select line, generally decoded from a row address value, connects each of a number of memory cells associated with the row address value to a pair of bit lines; each pair of bit lines are associated with a column of memory cells. During a read operation, the bit line pair communicates, to a sense amplifier or other output circuitry, a differential signal corresponding to the data state stored in the memory cell in its associated column which is also in the selected row. Conversely, during a write operation, the bit line pair communicates a differential signal from input circuitry to the memory cell in its associated column which is in the selected row.
An important factor in the performance of a particular memory circuit is the speed at which such read and write operations can be reliably performed. The reliability of such operations is improved where the differential signal communicated by the bit lines is as large as possible. For a read operation, the sense amplifier or other circuit can more accurately read the data state where the differential voltage between the bit lines is large. Especially where the memory cells are fabricated conventionally as cross-coupled inverters with resistive loads (the value of the resistors in the loads being as high as possible, for example on the order of Teraohms), noise immunity of the cell is improved by presentation of a large differential voltage on the bit lines during the write operation. Accordingly, the voltage swing of the bit lines in such memories is preferably as large as possible, occurring in as short a time as possible.
Conventional techniques for controlling the bit lines of such memory circuits to quickly accomplish voltage swings thereon include the precharging and equilibration (also referred to as equalization) of each bit line pair to a known voltage prior to each operation. The precharging and equilibration in such conventional techniques is performed by a clocked signal, which causes the precharge and equilibration for all bit lines at the same time, as described in as described in Minato, et al., "A 20 ns 64K CMOS SRAM", Digest of Technical Papers, 1984 IEEE International Solid-State Circuits Conference (IEEE, 1984), pp. 222-23. In this way, the bit lines will not have to make a full transition from one differential state to the other in successive cycles, significantly improving the performance of the circuit. Conventionally, the bit lines are precharged to a high voltage, such as the .sub.cc supply, and a transistor connected between the two bit lines in each pair is turned on to equilibrate the two bit lines, ensuring that they are precharged to the same voltage.
For a read operation in a static memory circuit as described hereinabove, it is desirable to precharge and equilibrate the bit lines to V.sub.cc, and then release the bit lines to respond to the memory cell in the selected row. The memory cell in the selected row will present a differential signal on the bit lines in the bit line pair, to communicate its stored data state. Release of the bit lines after precharge and equilibration allows the selected memory cell to establish this differential voltage without opposition from the precharge and equilibration of the bit lines. A conventional write operation is performed by a write circuit discharging one of the precharged bit lines in the bit line pair to ground. This is also preferably done after release of the precharge and equilibration of the bit lines, so that the write circuit also does not have to discharge a bit line in opposition to a static load attempting to pull the discharging bit line toward the precharge voltage.
An important write cycle timing parameter, particularly for static RAMs, is the time that valid input data must be present prior to the end of the write enable pulse; this parameter is commonly referred to as the data setup time. This timing parameter commonly affects the performance of the system incorporating the memories, as the data bus connected to the inputs of the memories will often not only carry input data thereto but will also carry data from the memories, or communicate data between other circuits in the system. As a result, system performance and flexibility is improved with short data setup times for the memory devices.
However, in many memories such as conventional SRAMs, significant parasitic resistance and capacitance may exist in the write paths between the external terminals of the device and the columns to which data is to be written. The effect of the parasitic impedance is, of course, to delay switching of nodes responsive to data applied thereto, such switching occurring as a result of change of data at the external terminals of the device Since the write operation is controlled by the end of the write enable pulse, valid input data must be present at all necessary internal nodes at such time as the end of the write enable pulse is communicated internally. Parasitic impedance in the write path thus affects the important parameter of data setup time, since the data setup time specification must account for the internal delay caused by parasitic impedance in the write path.
It is therefore an object of this invention to provide a circuit which reduces the data setup time during a write operation.
It is a further object of this invention to provide such a circuit which allows for late change of input data in a write operation.
It is a further object of this invention to provide such a circuit which operates in cooperation with column precharge and equilibration control in the memory.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.